Systems and methods for mitigation of resistor nonlinearity errors in single or multiphase switching voltage regulators employing inductor dcr current sensing

ABSTRACT

Systems and methods for mitigation of resistor nonlinearity errors in a power converter are provided. In at least one embodiment, the power converter comprises at least one power switch coupled to an input voltage, a pulse width modulation (PWM) circuit for generating control pulses for the at least one power switch, at least one output inductor coupled to a respective one of the at least one power switches, a current sensor coupled in parallel with the at least one output inductor, and at least one circuit element. The current sensor comprises at least one capacitor, at least one resistor for each of the at least one output inductors, and is coupled to the PWM circuit at a current bleed node. The at least one circuit element is coupled to the current bleed node and bleeds a bleed current from the current bleed node when a power switch is turned on.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a divisional of U.S. patent application Ser.No. 14/454,219 filed Aug. 7, 2014, now U.S. Pat. No. 9,912,234. Thisapplication also claims the benefit of U.S. Provisional Patent No.61/969,741, filed on Mar. 24, 2014, and U.S. Provisional PatentApplication Ser. No. 61/985,191, filed on Apr. 28, 2014, the contents ofall such applications hereby being incorporated herein by reference.

BRIEF DESCRIPTION OF THE DRAWINGS

Understanding that the drawings depict only exemplary embodiments andare not therefore to be considered limiting in scope, the exemplaryembodiments will be described with additional specificity and detailthrough the use of the accompanying drawings, in which:

FIGS. 1-3C are diagrams of examples systems used for mitigating theresistor nonlinearity; and

FIG. 4 is a block diagram of an example system including a powerconversion system that includes a circuit that mitigates resistornonlinearity.

In accordance with common practice, the various described features arenot drawn to scale but are drawn to emphasize specific features relevantto the exemplary embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown byway of illustration specific illustrative embodiments. However, it is tobe understood that other embodiments may be utilized and that logical,mechanical, and electrical changes may be made. Furthermore, the methodpresented in the drawing figures and the specification is not to beconstrued as limiting the order in which the individual steps may beperformed. The following detailed description is, therefore, not to betaken in a limiting sense.

Direct-current resistance (DCR) current sensing in a switching voltageregulator attempts to produce a voltage signal representing the currentthrough an inductor by processing and/or filtering the voltage dropacross the inductor. An example DCR current sensing circuit is describedin U.S. Pat. No. 5,982,160 and is incorporated herein by reference. Inembodiments that are multiphase voltage regulators where there is oneinductor per phase, the processing and/or filtering also containssumming elements such that the resulting voltage signal represents thesum of the currents in all the inductors. Additionally, the processingtypically contains a reactive circuit designed to match the timeconstant of the inductor's inductance and DCR such that the resultingoutput voltage signal is a true representation of the theoreticalvoltage drop across the inductor's DCR, but excludes the voltage dropacross the inductor's theoretical ideal inductance. With the appropriatescaling, this signal represents the current through the inductor(s). Asa result, the inductor current signal can be obtained withoutintroducing power dissipating sense elements into the inductor currentpath, such as by introducing a current-sense resistor in series with theinductor.

One embodiment of DCR current sensing includes, in addition to possiblyother elements, a low pass filter comprised of a resistor and capacitor.In some embodiments, for multi-phase regulators, there can be one filterresistor for each phase and a single common filter capacitor (ormultiple parallel capacitors forming a single filter capacitance) forall phases. In buck regulators for computing power, a relatively highvoltage drop can be applied across each filter resistor during therelatively brief “ontime” of each phase (i.e., the positive input supplyvoltage minus the positive output voltage), and a lower negative voltageis applied during the relative longer “off-time” of each phase (i.e.,the ground voltage-zero volts-minus the positive output voltage). Inmany embodiments, the ratio of the on-time to off-time voltages isrelatively high. In conventional implementations, the filter resistor isusually assumed to be constant (i.e., has the same value of electricalresistance) during both the on-time and the off-time. However, physicalresistors generally do not exhibit constant resistance in response tovarying applied voltage. That is, many physical resistors exhibit aslightly lower resistance when a high voltage is applied compared to aslightly higher resistance when a lower voltage is applied. Thisphenomenon is sometimes referred to as resistance nonlinearity, or isdescribed as a non-zero voltage coefficient of resistance. These termswill be used interchangeably throughout this disclosure. The effect ofthis nonlinearity in resistivity is an overemphasis in the filterresponse to the on-time compared to the offtime, which leads to anerroneous representation of the inductor current, typically biasedtoward a greater than true representation of the inductor current. Theembodiments described herein discuss a solution to this problem.

The systems and methods described below provide embodiments to mitigatethe current sense error that results from the nonlinear resistancevalues exhibited between high-voltage “on-states” and lower voltage“off-states” in direct-current resistance (DCR) current sensing. Theactual value of the resistance when the lower voltage is applied isherein referred to as the “nominal resistance” and the typically(although not necessarily) lower actual resistance while the highervoltage is applied will be referred to as the “diminished resistance”.This is due to the fact that at a higher voltage, the resistance of theresistor is typically lower.

FIG. 1 is a diagram of an example multi-phase system 100 used formitigating the resistor nonlinearity comprising an inductor DCR currentsensing network 101 a used in a single phase or multiphase voltageregulator coupled to pulse width modulation (PWM) controller integratedcircuit (IC) 101 b that provides for control for a voltage regulator(VR). This inductor DCR current sense system 101 a and PWM controller IC101 b are used only as examples of how the embodiments described belowcan be implemented into such a system 100. However, other systems 100can be used to implement the embodiments described below and more orless phases can be incorporated into the system 100. As stated above,this example system 100 can be used to mitigate the resistornonlinearity in inductor DCR current sensing. More specifically, aresistor denoted R_(BLEED) 102 is coupled from the node between theR_(SUM) resistor 104 and the capacitor C_(n) 106 to a switch 114.Moreover, in multi-phase systems 100, the system 100 has an OR gate 116,which activates R_(BLEED) 102 only when one or more phases are “on”. Insingle-phase embodiments, an OR gate 116 is not required. The OR gate116 is coupled from the voltage regulator phases's on-state controlsignals 118 to the switch 114, which will couple R_(BLEED) 102 to groundby activating the switch 114 when one or more of the phases's on-statecontrol signals 118 are on their “on” state. In an example, the switch114 can be an n-channel FET. Moreover, in some embodiments, the switch114 can be integrated into the pulse width modulation (PWM) controllerintegrated circuit (IC) 101 b. In some embodiments there may be leveltranslators between UGATE signals 118 and the logic level input signalsof OR gate 116. Furthermore, it is understood that the high sideswitching transistors may be p-channel MOSFETs (instead of the shownn-channel MOSFETs) and in this case there may be inverters between theUGATE signals 118 and the inputs of OR gate 116.

As a result of this configuration R_(BLEED) 102 draws current that,depending on the selection of R_(BLEED) 102, will be equivalent to theextra current resulting from the reduction of resistance in thefilter/summing resistors 104 of the system 100 during the on-time. Thisextra current results from the decreased resistance of resistors 104when a higher voltage is applied across the resistors 104. In someembodiments, the value of R_(BLEED) 102 is chosen such that the effectsof the resistor 104 nonlinearity are eliminated or sufficiently reducedin a nominal case. That is, in an exemplary embodiment, the idealpassive R_(BLEED) 102 can be selected by configuring the voltageregulator (VR) for the nominal condition of interest, and varying theR_(BLEED) 102 until the offset from the expected V_(OUT) 112 (due to thedesigned value of VR loadline resistance multiplied by the applied loadcurrent) has been reduced to zero. This ideal R_(BLEED) 102 value,however, can be highly dependent on operating conditions, as describedbelow, and therefore, a compromise correction can be chosen over therange of operating conditions and range of component parametricvariation so that at least acceptable (i.e., system specificationtolerance compliant) performance is achieved in all cases.

As mentioned above, there can be a number of conditions that influencethe nonlinearity of resistance due to varying voltage drops. Thoseconditions, which can be used to select R_(BLEED) 102, may include thevoltage coefficient of resistance with respect to voltage of the R_(SUM)resistors 104, the magnitude and variability of the V_(IN) 110, therange of programmed V_(OUT) 112, and the number of voltage regulatorphases that are enabled in all the supported power states.

The expected range of V_(IN) 110, in particular, can be important indetermining the viability of this embodiment, and the selection of theR_(BLEED) 102 value, because battery powered systems (e.g., notebookcomputers) can experience large variations in V_(IN) 110 ranging frombattery depleted to battery fully charged, and beyond if the system isoperating directly from the battery charging supply.

The programming of the V_(OUT) 112 has a smaller but stillnon-negligible effect on the nonlinearity error. The on-time voltageapplied to the R_(SUM) 104 resistors is V_(IN) 110-V_(ISUMP) 120, whichis approximately the same as V_(IN) 110-V_(OUT) 112. The off-time(negative) R_(SUM) 104 applied voltage is 0-V_(ISUMP) 120, againapproximately-V_(OUT) 112 since, in many embodiments, R₀'s 105 aretypically very small (i.e., 1-10 ohms, with very little current flowingthrough them). Since the resistor nonlinearity effect is due to thecomparative effective R_(SUM) 104 resistance in these two conditions,the resistor nonlinearity effect depends on both V_(IN) 110 and V_(OUT)112.

The number of active phases can also have an impact on the idealR_(BLEED) 102 value. All active phases contribute to the nonlinearityerror additively. However, any disabled phase will contribute no errorbecause the voltage drop across each phases respective RsuM 104 will bezero at all time during the switching cycle. With all phases enabled thegreatest bleed correction is required.

This system 100 accommodates changes in the number of active phases inmultiphase systems and to the changes in duty cycle, which may be due tochanging programmable V_(OUT) 112, varying V_(IN) 110, and system lossesdue to changes in ambient temperature and output load current. Changesin duty cycle resulting from load changes occur in all modes ofregulator operation, but are especially pronounced in Discontinuous Mode(DCM) operation; this embodiment directly addresses this cause ofcurrent sense error. More specifically, by applying a bleed resistance102 only when an active phase is in its “on” state, many of the designcompromises to accommodate varying operational conditions can beavoided. Since in most load and operational conditions, the on-times ofthe active phases are interleaved, the nonlinearity correction will beapplied proportionally to the number of active phases. Note that inresponse to large load and voltage programming transient events, therecan be times when multiple phases are in their on-state at the sametime; these episodes are typically infrequent and very brief because ofthe large ratio of V_(IN) 110 to V_(OUT) 112, reverting to only onephase active at a time for the majority of time. Despite the limitedutility in doing so, in some embodiments, a bleed resistor 102 can beincorporated into the system 100 for each phase, each with its ownswitch to ground, which is turned on when and only when that phase is inits on-state. This embodiment would correct the small and infrequenterror incurred with the single-resistor/switch approach whenevermultiple phases are in their on-states simultaneously.

The impact of duty cycle variation (in response to any cause, such asinput voltage, output voltage, load current, etc.) is accommodated bythe system 100 since the correcting R_(BLEED) 102 is applied only whilea phase is experiencing the high voltage resistor 104 nonlinearityduring its phase on-time. Any operating conditions that affect dutycycle will be ideally corrected, including DCM operation at low load. SoR_(BLEED) 102 is chosen to correct the erroneous extra current at itsactual amplitude only while it is occurring (during the on-time), ratherthan to bleed off that erroneous extra current averaged over the entireswitching cycle using an unswitched (permanently connected), typicallyhigh resistance bleed resistor. Because of the switched-resistorimplementation, the R_(BLEED) 102 can perhaps be 100 to 300 times thenominal R_(SUM) 104, rather than a much higher resistance value neededfor a permanently connected bleed resistor, another advantage inaddition to the duty-cycle and active phase count tracking behavior ofthe switched bleed resistor implementation.

FIG. 2A is a diagram of another example system 200 a used to mitigatethe resistor nonlinearity in inductor DCR current sensing. Thenon-labeled circuit elements in system 200 a (and systems 200 b-300 bbelow) can be similar to the circuit elements in system 100. In thisembodiment, a correcting bleed current is applied to the ISUMP node 230by a controlled current source 222 (which is dependent on a bleedcontrol current I_(BLEEDCONTROL) 232 and may scale the value ofI_(BLEEDCONTROL) 232 depending on its gain) when a phase's on-state isactive, as indicated by an on-state control signal 118 being in itson-state. The bleed current provided by the controlled current source222, as controlled by I_(BLEEDCONTROL) 232, is adjusted to match theeffect of the R_(SUM) 104 nonlinearity by continuously monitoring theerror induced by the R_(SUM) 104 nonlinearity, as determined by thenonlinearity of a model resistor, R_(MODEL) 224, of the same type as theR_(SUM) 104 resistors. Stated another way, the controlled “bleed”current source(s) 222 will be adjusted to subtract the current from theISUMP node 230 equal to the extra current from V_(IN) 110 to ISUMP 230during the on-time resulting from the reduction in the R_(SUM) 104resistance due to the resistor nonlinearity. The magnitude of this extracurrent will be determined by subtracting the modeled on-state R_(SUM)104 ideal current from the measured actual current. In some embodiments,for the atypical case that the resistor nonlinearity results in anincrease in actual resistance when a higher differential voltage isapplied, this discussion allows the computed bleed current to benegative. Due to the implementation of the bleed current in thisexample, unlike system 100, this system 200 a can automatically andcontinuously adjust to variations in the effect of the resistornonlinearity due to changing input and output voltage changes andcomponent parametric variations inherent in the resistor manufacturingprocess. As a result, this embodiment does not require the tuning orselection of the appropriate degree of mitigation as described in system100. Instead, it produces the best bleed current automatically.

As stated above, the bleed current provided by the controlled currentsource 222 is adjusted to match the effect of the R_(SUM) 104nonlinearity by continuously monitoring the error induced by thenonlinearity, as determined by the nonlinearity of a model resistor,R_(MODEL) 224, wherein R_(MODEL) 224 is chosen to be similar to R_(SUM)104. After which, the I_(BLEEDCONTROL) 232 fed into the controlledcurrent source 222, which controls the bleed current provided to theISUMP node 230, is adjusted to match the characterized nonlinearitycurrent of a representative model resistor, R_(MODEL) 224.

R_(MODEL) 224 can be chosen to possess two properties. First, R_(MODEL)224 can have the same nominal resistance to that of the R_(SUM) 104resistors. And second, R_(MODEL) 224 can have a voltage coefficientsimilar to that of the R_(SUM) 104 resistors; i.e., the nonlinearity ofR_(MODEL) 224 with respect to voltage can be similar to that of each andevery R_(SUM) 104 resistor. R_(MODEL) 224 can be assumed to besufficiently similar to the R_(SUM) 104 resistors in both nominalresistance and voltage nonlinearity if R_(MODEL) 224 is taken from thesame manufacturing lot as each and every R_(SUM) 104 resistor. Thisrequirement can be met if the manufacturing process mandates that bothR_(MODEL) 224 and each and every R_(SUM) 104 device be obtained from thesame component reel. If so, then the matching of the so-obtainedI_(BLEEDCONTROL) 232 will be accurate to the extent that the essentialparameters of resistors from the same reel are matched. Typically,actual resistance is within a specified tolerance of nominal resistance,which is typically 1% in computing power voltage regulator applications.While the nonlinearity of many formulations of resistors, such as thickfilm resistors, is not specified, there is an inherent similarity indevices manufactured from the same formulation by the same process, suchas resistors of the same nominal value provided in the same componentreel. As a result, the following derivation will assume that sufficientmatching of the essential resistor device parameters of all the R_(SUM)104 resistors and R_(MODEL) 224 has been obtained.

After R_(MODEL) 224 is chosen appropriately as described above, thenonlinearity of R_(SUM) 104 can be modeled by R_(MODEL) 224 in thefollowing way. V_(IN) 110 can be applied to the switched terminal 225 ofR_(MODEL) 224 via an internal switch 228 to V_(IN) 226. The otherterminal 227 of R_(MODEL) 224 is held at V_(ISUMP) 230 potential by atransconductance amplifier 228, and the amplifier current required to doso is stored as I_(From VIN) ^(actual) in I_(BLEED) COMPUTATION 234.Then, a ground 229 can be applied to the switched terminal 225 ofR_(MODEL) 224, again holding the other terminal 227 at V_(ISUMP) 230,and store the amplifier current required to do so as I_(ToGND). Thesetwo sequential operations can be repeated rapidly to maintain updatedamplitudes of these stored currents for further processing to produce ableed current reference that tracks the varying V_(IN) 110 and V_(ISUMP)230 voltages and the voltage dependent nonlinearity error. Theinstantaneous voltages V_(ISUMP) 230 and V_(IN) 110 can be used tocompute I_(BLEEDCONTROL) 232.

Once R_(MODEL) 224 is modeled after R_(SUM) 104, the I_(BLEEDCONTROL)232 can be derived as follows. First, the ideal on-time current can beestimated from VIN to ISUMP with the computational assumption that anidealized voltage-independent R_(SUM) 104 (or R_(MODEL) 224) during theon-time is equal to the measured R_(SUM) 104 (or R_(MODEL) 224) duringthe off-time, i.e. is equal to the “nominal” (for this operatingcondition) resistance value. This value is derived by noting that byOhm's law, V_(ISUMP) I_(ToGND)=R_(MODEL) 224. For the I_(ToGND)idealized voltage-invariant R_(MODEL) 224, V_(IN) 110−V_(ISUMP)230=I_(FromVIN) ^(ideal)×R_(MODEL) ^(ideal). Next, R_(MODEL) ^(ideal)can be eliminated (under the adopted convention that R_(MODEL)=R_(MODEL)^(ideal)) and solving for l_(FromVIN) ^(ideal) yields I_(FromVIN)^(ideal)=(V_(IN)−V_(ISUMP))×I_(ToGND)/V_(ISUMP). The desiredI_(BLEEDCONTROL) 232 will then be the difference between the measuredR_(MODEL) 224 current from VIN to ISUMP and the idealized, which yieldsI_(FromVIN) ^(ideal)×I_(BLEED)=I_(FromVIN) ^(actual)−I_(FromVIN)^(ideal), or I_(BLEED)=I_(FromVIN)^(actual)−(V_(IN)-V_(ISUMP))×I_(ToGND)/V_(ISUMP). This is the equationfor the I_(BLEEDCONTROL) 232 that can be computed using I_(BLEED)COMPUTATION 234, which controls the bleed current applied to the ISUMPnode 230 by the controlled current source 222 whenever any phase is inthe onstate. Note, this is only one example for I_(BLEED) COMPUTATION234 and other examples can be used for I_(BLEED) COMPUTATION 234 thattrack an estimate of the I_(BLEEDCONTROL) 232 for the instantaneousoperating conditions and the physical and electrical properties of theR_(SUM) 104 resistors.

In some embodiments, the controlled current source 222 is enabled onlywhen one or more phases are in their “on” states by coupling an ORswitch 116 from the phases's on-state control signals 118 to thecontrolled current source 222, and thus inheriting the duty-cycle andphase count tracking attributes of system 100. In other embodiments, thebleed current, as controlled by I_(BLEEDCONTROL) 232, can be applied bymultiple independent controlled current sources 222, which will applythe correct total current regardless of whether multiple phases are inthe on-state simultaneously, as shown in FIG. 2B. That is, a controlledcurrent source 222 is dedicated to each phase. The controlled currentsources 222 can be enabled only when each controlled current source's222 respective phase is in the on-state, as commanded by its on-statecontrol signal 118. Since the controlled current source or sources 222can be integrated into the controller, and are all connected to theISUMP node 230 within the PWM controller IC, multipleindependently-gated controlled current sources 222, one per phase in amultiphase regulator, can be used without increasing the number ofexternal interconnections required. Or, in some embodiments there can bemultiple controlled current sources 222, but fewer than the number ofphases, with each controlled current source 222 not necessarilydedicated to a particular phase, but instead, shared such that thenumber of controlled current sources 222 enabled simultaneously equalsthe number of phases in the on-state, up to the number of currentsources provided. These embodiments can eliminate the errors incurredduring the times when more than one phase is in its on-statesimultaneously, by applying the correct total bleed current for amultiplicity of on-state phases simultaneously for the duration of theirrespective on-times.

FIG. 3A is a diagram of another example system 300 a used to mitigatethe resistor nonlinearity in inductor DCR current sensing. In thisembodiment, the differential voltage V_(IN) 110-V_(ISUMP) 230 is appliedto a bleed current programming resistor, R_(PROG) 336, to produce areference current that varies proportionally as V_(IN) 110-V_(ISUMP) 230varies. This reference current will be scaled using an I_(BLEED) Scaler334 by a fixed ratio to produce the computed I_(BLEEDCONTROL) 332 whichdetermines the bleed current that will be drawn from the ISUMP node 230to correct for the R_(SUM) 104 nonlinearity. The bleed current switchingconcept of system 200 a, in which the correcting bleed current isapplied when one or more phases's on-state control signal 118 iscommanding its on-state, is also utilized in this embodiment. Therefore,in this embodiment, a nonlinearity correcting bleed current like that ofsystem 200 a and 200 b is rendered, except that this bleed current,which is controlled by I_(BLEEDCONTROL) 332, is functionally dependenton the varying value of V_(IN) 110 and V_(ISUMP) 230, and thusindirectly on the value of V_(OUT) 112. In embodiments which V_(IN) 110is a battery, this embodiment beneficially adjusts I_(BLEEDCONTROL) 332as V_(IN) 110 varies from the fully charged battery voltage (or possiblyhigher while the battery charging supply is in use), at which theR_(SUM) 104 nonlinearity error current is greatest, to the lowernearly-depleted battery voltage at which the R_(SUM) 104 nonlinearityerror current is at its lowest. In some embodiments, R_(PROG) 336 mightbe selected to be the value that best corrects the R_(SUM) 104nonlinearity error of a representative system at an intermediate valueof V_(IN) 110 and that I_(BLEEDCONTROL) can vary favorably as V_(IN) 110deviates from that intermediate value.

Similar to systems 200 a and 200 b, this embodiment 300 a allowsI_(BLEEDCONTROL) 332 to still adapt to changes in the input voltage 110and output voltage 112. The system designer can determine empiricallythe nominal (and assumed fixed) extent of R_(SUM) 104 voltagecoefficient of resistance nonlinearity error to be corrected. In doingso, the voltage coefficient of resistance of the R_(SUM) resistors 104is assumed to be essentially invariant, where a designer can thendetermine what the nominal voltage coefficient of resistance will be.Moreover, one can assume that the value of the resistance of the R_(SUM)resistors 104 can be assumed to be constant over the expected range ofthe setting of the regulator output voltage 112. This assumption isoften valid since the full range of output voltage 112 settingstypically vary little compared the switching regulator input voltage110, and thus, the variation of voltages applied to the resistivematerial may be sufficiently low to permit an assumption of constantvoltage coefficient of resistance over this range of operatingconditions.

Similar to system 200 a, in some embodiments, the controlled currentsource 222 in system 300 a is enabled only when one or more phases arein their “on” states by coupling an OR switch 116 from the phases'son-state control signals 118 to the controlled current source 222, andthus inheriting the duty-cycle and phase count tracking attributes ofsystems 100 and 200 a. In other embodiments, and similar to system 200b, the bleed current can be applied by multiple independent currentsources 222, which will apply the correct total current when multiplephases are in the on-state simultaneously, as shown in FIG. 3B. Thecontrolled current sources 222 can then be enabled only when eachcontrolled current source's 222 respective phase is in its on-state, asindicated by its on-state control signal 118. Since the controlledcurrent source or sources 222 can be integrated into the controller, andare all connected to the ISUMP node 230 within the controller, multipleindependently-gated controlled current sources 222, one per phase in amultiphase regulator, can be used without increasing the number ofexternal interconnections required. Or, in some embodiments there can bemultiple controlled current sources 222, but fewer than the number ofphases, with each controlled current source 222 not necessarilydedicated to a particular phase, but instead, shared such that thenumber of controlled current sources 222 enabled simultaneously equalsthe number of phases in the on-state, up to the number of currentsources provided. These embodiments might be useful in the case that amultiphase regulator may require that in response to changing outputvoltage setting or in response to load transient events, multiple phasesare in the on-state simultaneously. These embodiments can eliminate theerrors incurred during the times when more than one phase is in itson-state simultaneously, by applying the correct total bleed current fora multiplicity of on-state phases simultaneously for the duration oftheir respective on-times.

In some other embodiments, the external bleed current programmingresistor, R_(PROG) 336, in FIGS. 3A and 3B can be replaced by aninternal current reference devised to be proportional to V_(IN)110-V_(ISUMP) 230, with the proportionality determined by a programmablescaling factor 338 via a digital programming interface, to produce theI_(BLEEDCONTROL) 332, as shown in FIG. 3C. In some embodiments, thedigital programming interface can be a serial communication bus or otherprogramming interface. The bleed current, as controlled byI_(BLEEDCONTROL) 332, is then applied to the ISUMP node 230 as a bleedcurrent when one or more switching phases are in their onstate bycoupling an OR switch 116 from the phases's on-state control signals 118to the controlled current source 222 or by having multipleindependently-gated controlled current sources 222, one per phase in amultiphase regulator (not shown).

Replacing R_(PROG) 336 with a V_(IN) 110-V_(ISUMP) 230 proportionalreference current and programmable scaling factor 338 has the advantageof not requiring any additional external connections to the PWMcontroller IC 101 b, which can be a valuable attribute in systems forwhich input/output connections are scarce. It also allows programming ofthe nonlinearity correction via PWM controller IC 101 b initializationfirmware, which may permit adjustment of the nonlinearity correction inresponse to configuration data representing the hardware implementationthroughout the manufacturing lifetime of the PWM controller IC 101 b.

In the case of a power management integrated circuit (PMIC) containingmultiple voltage regulators (each either single or multi-phase), theR_(PROG) 336 interconnection and I_(BLEED) computational or scalingcircuitry and programming 234 or 334 or any resources required for anyembodiment described above can be shared by all voltage regulators byreplacing the connection to a voltage reference of a particularregulator's I_(SUMP) node 230 with a connection to a common referencevoltage, such as a resistive average of all regulators' I_(SUMP) nodes230 or the average of all the command reference voltages. Since thedifferent output voltages 112 of the multiple voltage regulators in aPMIC are typically similar in amplitude when compared to the differencebetween any particular output voltage 112 and the (typically) commoninput voltage 110, the deviation of the commonly derivedI_(BLEEDCONTROL) 232 and 332 from the ideal bleed current for any ofthem is likely to be small.

In other embodiments for a PMIC, a common means of programming aI_(BLEEDCONTROL) 232 and 332 reference can be utilized that may bedirectly responsive to common V_(IN) 110, but may be applied to eachvoltage regulator according to a functional dependence on the programmedoutput voltage 112, or sensed output voltage (such as at the ISUMP node230 or ISUMN node 221) of each voltage regulator. Such means wouldcompensate, by some functional relationship of each regulator's outputvoltage 112 to the derived common reference I_(BLEEDCONTROL) 232 and332, for the difference in output voltage 112 provided by each voltageregulator. This compensation may also be directed and scaled for eachvoltage regulator via the PMIC's serial interface bus with the hostprocessor commanding the PMIC. The advantage so obtained would be abetter approximation of the ideal I_(BLEEDCONTROL) 232 and 332mitigation to be applied to each voltage regulator without theadditional cost (in circuit size, and especially in addedinterconnections) required for fully individualized programming of eachvoltage regulator's I_(BLEEDCONTROL) 232 and 332, compared to fullyindependent bleed current programming.

For any PMIC method in which the derivation/computation of theI_(BLEEDCONTROL) 232 and 332 includes mechanisms that are shared inwhole or in part by more than one voltage regulator, the switchingmeans, whereby the bleed current (or multiplicity of bleed currents) isapplied to each respective ISUMP node 230 whenever a voltage regulator'sphase is in the on-state, should still be provided individually andindependently for each voltage regulator. Doing so provides all of theduty cycle and phase count tracking advantages of systems 100-300 b atlittle or no additional cost, because all such required interconnectionsand replication of bleed current sources can be made internally to thePMIC.

FIG. 4 is a block diagram of an example system 400 including a powerconversion system 402 that includes a circuit 403 that mitigatesresistor nonlinearity. System 400 includes one more power conversionsystems 402 coupled to one or more processing devices 404 and one ormore memory devices 406. The one or more power conversion systems 402can receive unregulated power (e.g., line power, battery), regulate thepower, and provide regulated power to the one or more processing devices404 and one or more memory devices 406. In at least one embodiment, thepower conversion system 402 is implemented as one or more of the powerconverters 100-300 c with at least one circuit element 403 thatmitigates resistor non-linearity errors as discussed above in FIGS. 1-3C. In an embodiment, the one or more processing devices 404 can includea central processing unit (CPU), microcontroller, microprocessor (e.g.,a digital signal processor (DSP)), field programmable gate array (FPGA),application specific integrated circuit (ASIC), or other processingdevice. Moreover, in an embodiment, the one or more memory devices 406can include a conventional hard disk, volatile or non-volatile mediasuch as a solid state hard drive, random access memory (RAM) including,but not limited to, synchronous dynamic random access memory (SDRAM),double data rate (DDR) RAM, RAMBUS dynamic RAM (RDRAM), static RAM(SRAM), etc.), electrically erasable programmable ROM (EEPROM), andflash memory, etc. The one or more processing devices 404 can becommunicatively coupled to the one or more memory devices 406.

In other examples, such a power conversion system 402 can provideregulated power to other functional circuits instead of or in additionto one or more processing devices 404 and one or more memory devices406. For example, such a power conversion system 402 can provide powerto internal device components, peripheral devices, or other components.Such a power conversion system 402 can be included in any suitableelectronic device using regulated power such as a desktop, laptop, ortablet computer, a set top box, battery charger, or other device.

Example Embodiments

Example 1 includes a power converter comprising: at least one powerswitch coupled to an input voltage; a pulse width modulation circuit forgenerating control pulses for the at least one power switch; at leastone output inductor, wherein each of the at least one output inductorsis coupled to a respective one of the at least one power switches; acurrent sensor coupled in parallel with the at least one output inductorfor sensing current passing through all of the at least one outputinductors, wherein the current sensor comprises at least one resistorfor each of the at least one output inductors and at least onecapacitor, and wherein the current sensor and the pulse width modulationcircuit are coupled together at a current bleed node; and at least onecircuit element coupled to the current bleed node, wherein the at leastone circuit element bleeds a bleed current from the current bleed nodewhen one or more of the at least one power switches is turned on.

Example 2 includes the power converter of Example 1, wherein the atleast one circuit element is a bleed resistor and wherein when the pulsewidth modulation circuit generates a turn-on pulse for the at least onepower switch the bleed resistor is coupled to ground via a switch.

Example 3 includes the power converter of any of Examples 1-2, whereinthe at least one circuit element is at least one current controlledcurrent source and wherein the bleed current is a current substantiallyproportional to the at least one resistor's resistance nonlinearity.

Example 4 includes the power converter of Example 3, wherein the bleedcurrent is a positive current.

Example 5 includes the power converter of any of Examples 3, wherein thebleed current is a negative current.

Example 6 includes the power converter of any of Examples 3-5, whereinthe bleed current is computed using a model resistor's resistancenonlinearity.

Example 7 includes the power converter of any of Examples 3-6, whereinthe bleed current is dependent on a programmable scaling factor.

Example 8 includes a controller for a power converter, the controllercomprising: a current sense input; a current sense circuit coupled tothe current sense input at a current bleed node, wherein the currentsense input monitors the current output of the power converter; a pulsewidth modulation circuit that generates control signals for at least onepower switch that is coupled to an input voltage and is coupled to arespective output inductor, wherein the pulse width modulation circuitis configured to regulate an output voltage of the power converter; andat least one circuit element coupled to the current bleed node, whereinthe at least one circuit element bleeds a bleed current from the currentbleed node when one or more of the at least one power switches in thepower converter is turned on.

Example 9 includes the pulse width modulation circuit of Example 8,wherein the at least one circuit element is a bleed resistor and whereinwhen the pulse width modulation circuit generates a turn-on signal forthe at least one power switch and the bleed resistor is coupled toground via a switch.

Example 10 includes the pulse width modulation circuit of any ofExamples 8-9, wherein the at least one circuit element is at least onecurrent controlled current source and wherein the bleed current is acurrent substantially proportional to at least one resistor's resistancenonlinearity.

Example 11 includes the pulse width modulation circuit of Example 10,wherein the bleed current is a positive current.

Example 12 includes the pulse width modulation circuit of any ofExamples 10, wherein the bleed current is a negative current.

Example 13 includes the pulse width modulation circuit of any ofExamples 10-12, wherein the bleed current is computed using a modelresistor's resistance nonlinearity.

Example 14 includes the pulse width modulation circuit of any ofExamples 10-13, wherein the bleed current is dependent on a programmablescaling factor.

Example 15 includes a method comprising: generating control signals forat least one phase of a power converter; monitoring the control signalsto determine whether one or more of the at least one phase in the powerconverter is turned on; and bleeding a bleed current from a currentbleed node in the power converter when one or more of the at least onephase is turned on.

Example 16 includes the method of Example 15, wherein bleeding a currentcomprises bleeding a current that is substantially proportional to amodel resistor's resistance nonlinearity.

Example 17 includes the method of any of Examples 15-16, whereinbleeding a bleed current comprises bleeding a bleed current that isdependent on a programmable scaling factor.

Example 18 includes the method of any of Examples 15-17, whereinbleeding a bleed current comprises bleeding a current using a resistorwhen one or more of the at least one phase is turned on.

Example 19 includes the method of any of Examples 15-18, whereinbleeding a bleed current comprises bleeding a current using at least onecurrent controlled current source when one or more of the at least onephase is turned on.

Example 20 includes the method of Example 19, wherein generating controlsignals comprises generating control signals for each of at least onephases of a power converter, the power converter having a plurality ofphases and wherein bleeding a bleed current from a current bleed nodecomprises using a plurality of current controlled current sources, eachof the plurality of current controlled current sources are used for arespective one of the plurality of phases.

Example 21 includes the method of any of Examples 19-20, whereinbleeding a bleed current comprises bleeding a positive current.

Example 22 includes the method of any of Examples 19-20, whereinbleeding a bleed current comprises bleeding a negative current.

Example 23 includes an electronic device comprising: one or moreprocessing devices; one or more memory devices communicatively coupledto the one or more processing devices; and one or more power conversionsystems coupled to the one or more processing devices and the one ormore memory devices, the one or more power conversion systems including:at least one circuit that mitigates resistor non-linearity errors in theone or more power conversion systems.

Example 24 includes the electronic device of Example 23, wherein the atleast one circuit is coupled to a current bleed node in the one or morepower conversion systems and wherein that at least one circuit bleeds ableed current from the current bleed node when the one or more powerconversion systems is turned on.

Example 25 includes the electronic device of Example 24, wherein the atleast one circuit is a bleed resistor and wherein when the one or morepower conversion systems is turned on the bleed resistor is coupled toground via a switch.

Example 26 includes the electronic device of any of Examples 24-25,wherein the at least one circuit is at least one current controlledcurrent source and wherein the bleed current is a current substantiallyproportional to at least one resistor's resistance nonlinearity includedin the one or more power conversion systems.

Example 27 includes the electronic device of Example 26, wherein thebleed current is computed using a model resistor's resistancenonlinearity.

Example 28 includes the electronic device of any of Examples 26-27,wherein the bleed current is dependent on a programmable scaling factor.

Example 29 includes the method of any of Examples 26-28, whereinbleeding a bleed current comprises bleeding a positive current.

Example 30 includes the method of any of Examples 26-28, whereinbleeding a bleed current comprises bleeding a negative current.

Example 31 includes the electronic device of any of Examples 23-30,wherein the electronic device comprises one of desktop, laptop, ortablet computer, a set top box, or a battery charger.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement, which is calculated to achieve the same purpose,may be substituted for the specific embodiments shown. Therefore, it ismanifestly intended that this invention be limited only by the claimsand the equivalents thereof.

What is claimed is:
 1. A power converter comprising: at least one powerswitch coupled to an input voltage; a pulse width modulation circuit forgenerating control pulses for the at least one power switch; at leastone output inductor, wherein each of the at least one output inductorsis coupled to a respective one of the at least one power switches; acurrent sensor coupled in parallel with the at least one output inductorfor sensing current passing through all of the at least one outputinductors, wherein the current sensor and the pulse width modulationcircuit are coupled together at a current bleed node; and at least onecircuit element coupled to the current bleed node, wherein the at leastone circuit element bleeds a bleed current from the current bleed nodewhen one or more of the at least one power switches is turned on.
 2. Thepower converter of claim 1, wherein the at least one circuit element isa bleed resistor and wherein when the pulse width modulation circuitgenerates a turn-on pulse for the at least one power switch the bleedresistor is coupled to ground via a switch.
 3. The power converter ofclaim 1, wherein the at least one circuit element is at least onecurrent controlled current source and wherein the bleed current is acurrent substantially proportional to the at least one resistor'sresistance nonlinearity.
 4. The power converter of claim 3, wherein thebleed current is a positive current.
 5. The power converter of claim 3,wherein the bleed current is a negative current.
 6. The power converterof claim 3, wherein the bleed current is computed using a modelresistor's resistance nonlinearity.
 7. The power converter of claim 3,wherein the bleed current is dependent on a programmable scaling factor.8. The power converter of claim 1, wherein the current sensor comprisesat least one resistor for each of the at least one output inductors andat least one capacitor.
 9. A controller for a power converter, thecontroller comprising: a current sense input; a current sense circuitcoupled to the current sense input at a current bleed node, wherein thecurrent sense input monitors the current output of the power converter;and at least one circuit element coupled to the current bleed node,wherein the at least one circuit element bleeds a bleed current from thecurrent bleed node when one or more of the at least one power switchesin the power converter is turned on.
 10. The controller of claim 9,further comprising: a pulse width modulation circuit that generatescontrol signals for at least one power switch that is coupled to aninput voltage and is coupled to a respective output inductor, whereinthe pulse width modulation circuit is configured to regulate an outputvoltage of the power converter, wherein the at least one circuit elementis a bleed resistor and wherein when the pulse width modulation circuitgenerates a turn-on signal for the at least one power switch and thebleed resistor is coupled to ground via a switch.
 11. The controller ofclaim 9, wherein the at least one circuit element is at least onecurrent controlled current source and wherein the bleed current is acurrent substantially proportional to at least one resistor's resistancenonlinearity.
 12. The controller of claim 11, wherein the bleed currentis a positive current.
 13. The controller of claim 11, wherein the bleedcurrent is a negative current.
 14. The controller of claim 11, whereinthe bleed current is computed using a model resistor's resistancenonlinearity.
 15. The controller of claim 11, wherein the bleed currentis dependent on a programmable scaling factor.
 16. An electronic devicecomprising: one or more processing devices; one or more memory devicescommunicatively coupled to the one or more processing devices; and oneor more power conversion systems coupled to the one or more processingdevices and the one or more memory devices, the one or more powerconversion systems including: at least one circuit that mitigatesresistor non-linearity errors in the one or more power conversionsystems, wherein the at least one circuit is coupled to a current bleednode in the one or more power conversion systems and wherein that atleast one circuit bleeds a bleed current from the current bleed nodewhen the one or more power conversion systems is turned on.
 17. Theelectronic device of claim 16, wherein the at least one circuit is ableed resistor and wherein when the one or more power conversion systemsis turned on the bleed resistor is coupled to ground via a switch. 18.The electronic device of claim 16, wherein the at least one circuit isat least one current controlled current source and wherein the bleedcurrent is a current substantially proportional to at least oneresistor's resistance nonlinearity included in the one or more powerconversion systems.
 19. The electronic device of claim 18, wherein thebleed current is computed using a model resistor's resistancenonlinearity.
 20. The electronic device of claim 18, wherein the bleedcurrent is dependent on a programmable scaling factor.